The present invention relates generally to the fabrication of semiconductor devices, and more particularly the formation of contact structures in a semiconductor device.
Integrated circuits can typically include various layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) may be formed. Gates for insulated gate field effect transistors may be formed from a deposited semiconductor material. Such active devices. may then be connected to one another by one or more conductive or semiconductive layers. The interconnecting conducting layers may be separated from one another by insulating layers.
Insulating layers typically provide electrical isolation between conductive and/or semiconductive layers. Conductive or semiconductive layers may be formed from a single layer of material, or alternatively, include one or more conductive (or semiconductive) materials.
Different conductive or semiconductive layers can be connected to one another by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, contacts can connect a substrate to a conductive or semiconductive layer, while a via can connect two different conductive or semiconductive layers to one another.
Layers may be patterned by lithography and etch steps. For example, a lithography step can form an interconnect etch mask over a conductive and/or semiconductive layer. An etch step can then transfer the interconnect etch mask pattern to the conductive and/or semiconductive layer. A lithography step can also form a contact hole etch mask over an insulating layer. An etch step can then form a contact hole through the insulating layer.
One concern with certain contact structures can be the alignment of a contact with a lower conductive and/or semiconductor layer. Because a contact can be formed by etching a hole through an insulating layer to an underlying conductive or semiconductive layer, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer. However, because the sizes of features in modern integrated circuits can be so small, some misalignment can be inherent in a manufacturing process.
Another concern with certain contact structures can be the alignment of an intermediate layer with respect to an underlying layer. As but one example, a contact hole may have to be formed adjacent to, or overlap, a transistor gate layer. In the event such a gate is misaligned with respect to an underlying layer, the available area exposed by a contact hole can be reduced.
Yet another concern with certain contact structures can be variations in the dimensions of an intermediate layer. As but one example, a transistor gate layer may have a certain critical dimension (CD) range. In the event such a gate layer is at the high end of such a range, the gate layer may cover more available contact area than nominal or low CD ranges. This can be exacerbated by complex gate structure shapes. Many times, complex gate structure shapes can contribute to increasing the compactness of a circuit.
A number of examples will now be described to further illustrate the effect of misalignment and CD variations on the formation of certain contacts.
FIGS. 10A and 10B are top plan views showing an example of a conventional mask set and a corresponding contact formation method. In particular, FIG. 10A shows three overlapping mask patterns, each distinguished by a particular hatching pattern.
A first mask is an xe2x80x9cactivexe2x80x9d mask 1000. An active mask 1000 can be used to form an xe2x80x9cactivexe2x80x9d area in a substrate. For example, an active mask 1000 can be used to form isolation structures, such as shallow trench isolation (STI) structures or those formed with local oxidation of silicon (LOCOS) methods.
A second mask can be a gate mask 1002. A gate mask 1002 can be used form a gate layer pattern over an active area. A gate mask 1002 may pattern a layer that forms the gate of a transistor. Such a layer may inherently connect two or more transistor gates and/or connect a transistor gate to the substrate (by a xe2x80x9cburiedxe2x80x9d contact or another such contact).
FIG. 10A also includes a contact hole mask 1004. A contact hole mask 1004 can be used to form a contact hole to a substrate. (or another conductive layer). The particular contact hole mask 1004 of FIG. 10A can be for a xe2x80x9cself-alignedxe2x80x9d contact. A self-aligned contact may eliminate a minimum spacing requirement from a gate mask 1002.
FIGS. 10A and 10B also include a direction indicator that shows a Y direction and an X direction. The Y and X directions are perpendicular to one another.
FIG. 10B shows an example of a semiconductor device that can be formed with the masks of FIG. 10A. FIG. 10B shows a substrate 1006 that can include active areas 1008 formed therein. A gate layer structure 1010 may be formed on a substrate 1006 and over portions of active areas 1008. It is noted that a misalignment of the gate layer structure 1010 with respect to the contact hole mask 1004 in the positive Y direction can reduce overall available contact area, as a resulting gate layer structure 1010 can extend into a contact hole 1012 location.
Variations in gate layer structure 1010 CDs can also impact contact area. For example, a gate layer structure 1010 with a high CD can extend into a contact hole location, reducing contact area.
Misalignment between a contact hole mask 1004 and active areas 1008 can also impact contact area. In the example of FIGS. 10A and 10B, a misalignment of a contact hole mask 1004 with respect to an active area 1008 in the positive or negative X direction can reduce overall available contact area, as a resulting contact hole 1012 can overlap isolation regions in a substrate 1006.
FIGS. 10A and 10B also show one example of how a mask pattern transfers to an underlying device structure. For example, while a contact hole mask 1004 may have a square shape, xe2x80x9cedgexe2x80x9d and/or xe2x80x9ccornerxe2x80x9d lithography and etch effects can give rise to a resulting contact hole 1012 with a circular shape. Further, while a gate mask 1002 may include sharp stepped features, such as those shown as item 1014 in FIG. 10A, such features can be smoothed out in a lithography and etch step, resulting in a more gradually contoured structure, such as the gate layer structure 1010 of FIG. 10B.
A second conventional example of a mask set and contact formation method are shown in FIGS. 11, 12A to 12C and 13A to 13C. FIG. 11 is an example of a mask set that may be used to form a xe2x80x9ccactusxe2x80x9d contact hole. FIGS. 12A to 12C are top plan views illustrating a semiconductor structure that may be manufactured with the mask set of FIG. 11. FIGS. 13A to 13C are side cross-sectional views corresponding to the views of FIGS. 12A to 12C.
A cactus contact hole can be a contact hole formed adjacent to a cactus shaped intermediate structure. An intermediate structure can potentially extend into a contact hole location, reducing overall contact area. A cactus structure can include a first portion that extends in one direction and a second portion that extends from the first portion at an angle. A cactus contact derives its name from the shape of the intermediate structure, which can, in some configurations, resemble a Saguaro-type cactus. A first portion may correspond to a cactus body while a second portion may correspond to a cactus arm.
A cactus contact hole can be a contact hole that is formed between a body portion and an arm portion of a cactus shaped intermediate structure.
FIG. 11 shows three overlapping mask patterns, each distinguished by a particular hatching pattern. The masks can include an xe2x80x9cactivexe2x80x9d mask 1100, a gate layer mask 1102, and a contact hole mask 1104. A gate layer mask 1102 includes a first section 1106 that extends in the vertical direction of FIG. 11 and a second section 1108 that extends at an angle to a first section 1106.
As shown by FIG. 11, a contact hole mask 1104 can be situated to form a contact hole generally between a first portion 1106 and a second portion 1108.
FIGS. 12A to 12C show a sequence of steps in the formation of a contact hole with the masks of FIG. 11. In particular, FIG. 12A shows an active area 1200 formed in a substrate 1202. FIG. 12A also includes an arrowed line that indicates the side cross sectional view of FIG. 13A.
FIG. 13A shows a substrate 1202 as well as an active area 1200. An active area 1200 may be surrounded by isolation regions 1300. Isolation regions 1300 may be formed with STI or LOCOS methods, to name but two possible examples.
FIG. 12B shows a xe2x80x9ccactusxe2x80x99 gate layer structure 1204 formed over a substrate 1202 according to gate layer mask 1102. In the particular example of FIGS. 12A to 12C, a gate layer structure 1204 is misaligned in the positive Y direction, and further, has a high CD.
It is noted that xe2x80x9ccactusxe2x80x9d gate layer structures can be particularly desirable as such structures can be used in many common circuit elements, such as a complementary metal-oxide-semiconductor (CMOS) inverter, for example. In such an arrangement, a first portion 1206 can form commonly connected gates of an n-channel MOS transistor and a p-channel MOS transistor. A second portion 1208 can be connected to a node that drives the commonly connected gates.
A cactus shaped gate layer structure 1204 can include a xe2x80x9chigh CDxe2x80x9d corner 1210 formed by an intersection of a first portion 1206 and a second portion 1208. In a high CD corner 1210, due to undesirable lithographic and etch effects, it may be difficult to remove all material indicated by a mask. This can allow such material to extend into an adjacent contact hole location, reducing contact area.
FIG. 12B also includes an arrowed line that indicates the side cross sectional view of FIG. 13B.
FIG. 13B shows a gate layer structure 1204. A gate layer structure 1204 may include a gate layer 1302, sidewalls 1304, and a top isolation 1306. Such an arrangement may allow for self-aligned contact structures.
FIG. 12C shows a contact hole 1212 that may be formed according to contact hole mask 1104. As shown by FIG. 12C, misalignment between a contact hole 1212 and an underlying gate layer structure 1204 and/or a high CD can result in undesirable reductions in contact area. FIG. 12C can also illustrates how available contact area (i.e., portions of active area 1200 in the high CD corner 1210) may not be used efficiently. In particular, in the example of FIG. 12C, unused contact area may be available above contact hole 1212 in the positive Y direction. FIG. 12C also includes an arrowed line that indicates the side cross sectional view of FIG. 13C.
FIG. 13C shows a contact hole 1212 that may be formed through an interlayer insulation layer 1308. As noted above, and as shown in FIG. 13C, conventional approaches can result in contact with high resistance or contacts that fail. FIG. 13C shows a contact that fails. One example of a failure is a contact etch that may fail to expose active area 1200. Another possible failure is that a conductive contact material 1310 may fail to make contact with active area 1200. (A conductive contact material 1310 is not shown in FIG. 12C.)
Thus, conventional approaches to forming a contact hole adjacent to a cactus gate layer structure can be adversely affected by misalignment variation and/or CD variations and/or corner and other lithographic effects.
It would be desirable to arrive at some way of forming contact holes adjacent to intersecting portions of an underlying layer, such as a cactus gate layer structure, that can provide for greater contact area.
The present invention includes embodiments having a xe2x80x9ccactusxe2x80x9d contact hole that may be formed with a contact hole mask. A cactus contact hole mask may include at least one corner extension that can result in greater contact area. More particularly, a contact hole mask may have a generally rectangular structure having four corner extensions. A contact hole mask may also include side indents.
According to one aspect of the embodiments, a semiconductor structure can include an active area that extends in a first direction. A cactus contact hole may be formed with a contact hole mask having a generally rectangular shape. A longer dimension of the rectangular shape may extend in the first direction.
According to another aspect of the embodiments, cactus structures may be formed that are intermediate to a contact hole. Each cactus structure may include a structure corner formed by the intersection of a first portion and a second portion. A structure corner may be formed by an intermediate layer mask having at least one corresponding corner indent.
According to another aspect of the embodiments, first portions of intermediate cactus structures may form gates for complementary insulated gate field effect transistors, such as metal-oxide-semiconductor (MOS) transistors.
According to another aspect of the embodiments, second portions of adjacent intermediate cactus structures may face one another for a compact static random access memory cell arrangement.